As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed from portions of the vertical semiconductor fin extending from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device.
The ability to fabricate vertical semiconductor fins having uniform profiles has proven to be challenging and non-trivial using current FinFET process technologies. For example, fin fabrication using standard multi-patterning methods such as sidewall image transfer (SIT), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) techniques, for example, are problematic with regard to process control issues, which typically result in variations in the critical dimensions of mandrel and spacer features, and thereby resulting in semiconductor fin width variations. Furthermore, the use of dry etch plasma methods such as reactive ion etching (ME) to pattern semiconductor fins from semiconductor layers can be problematic as ME methods exhibit etch selectivity with regard to vertical semiconductor fins made of different materials (e.g., silicon (Si) for n-type FinFETS, and silicon germanium (SiGe) for p-type FinFETS), which results in fin width variations in different device regions.
Furthermore, there are limitations on the minimum semiconductor fin width which can be achieved (e.g., semiconductor fin width no less than 8-9 nm) using current semiconductor fin fabrication techniques based on SIT and ME. In some applications, however, it is desirable to fabricate semiconductor fins with thinner profiles (e.g., less than 8 nm) to enhance electrical properties of the FinFET devices (e.g., increase voltage threshold and decrease DIBL (drain-induced barrier lowering), etc.). To achieve thinner fin width profiles, a trimming process can be used to laterally etch the sidewalls of the vertical semiconductor fins to reduce fin width. However, current fin trimming techniques are also problematic with regard to their inability to achieve conformal trimming due to, e.g., different etch selectivities of the semiconductor fin materials, and micro-loading effects which result in a vertical etch rate of the semiconductor fin height which is greater than a lateral etch rate of the semiconductor fin width, which results in both unequal height and unequal widths of semiconductor fins.